Digital Decimation Filter Using FPGA Board.

Our task is to describe in VHDL, Test, and implement a DSP circuit called Decimation Filter. This one has two main sections: the CIC section and the FIR section.

Even the CIC and the FIR filters are composed of many sections thats we are going to describe them one by one.

Both sections consist of N stages each. The exact structure of each stage, and the way of connecting all stages together are presented below in this article today.

So let's start by introducing a Decimation filter.
A Decimation Filter is one of the most used filters in signal processing and noise avoiding sustems.

Basically a decimator is a digital low pass filter, which also include the operation of sample rate reduction. He does operation of noise shaping and hence the noise is pushed to higher frequencies so that the decimation stage following the modulator can filter out this noise above the cutoff frequency.

The band limited signal can then be resampled by discarding X – 1 samples out of every X samples, where X being the oversampling ratio. By averaging X samples out of the quantized sigma-delta output.
The decimation filter achieves a high output resolution and also the frequency of the output data is at twice the input signal bandwidth which is the nyquist rate.
So to concluse how decimator filter work:

This is our input signal X(n):

   

We want to decimate this signal wiith decimation ratio R = 2.

This means thats we are going to generate a Y(n) decimation response of X(n) with the half frequency of X(n) = 0.5 Hz.

In digital signal processing, decimation is the process of reducing the sampling rate of a signal. Complementary to interpolation, which increases sampling rate, it is a specific case of sample rate conversion in a multi-rate digital signal processing system. Decimation utilises filtering to mitigate aliasing distortion, which can occur when simply downsampling a signal. A system component that performs decimation is called a decimator.

So Decimation filter is a low pass filter able to decrease sampling rate, it is composed by mixing a CIC Filter with a Fir Filter.

Cascaded integrator–comb filter :CIC Filter

A CIC filter consists of one or more integrator and comb filter pairs. In the case of a decimating CIC, the input signal is fed through one or more cascaded integrators, then a down-sampler, followed by one or more comb sections (equal in number to the number of integrators). An interpolating CIC is simply the reverse of this architecture, with the down-sampler replaced with a zero-stuffer (up-sampler).

Where:

R = decimation or interpolation ratio

M = number of samples per stage (usually 1 but sometimes 2)

N = number of stages in filter

Characteristics of CIC Filters

1. Linear phase response;
2. Utilize only delay and addition and subtraction; that is, it requires no multiplication operations

CIC Filter is composed by mixing integrators,comb blocks with frequency dividers.

Integrator:

A digital integrator block is a block who add the previous result with present input to generate present output so simply :

  Y(n) = Y(n-1) + X(n) 

To create this block in VHDL, you have to use an intelligent way in program who help you to control your input signal delayed and to avoid critical value who could generate incorrect result specially when we look for Y(0).

Comb:

 The principal function of a comb filter is mixing a delayed version of a signal to itself.

Y(n) = X(n) + X(n-RM)

When both R and M are positive constants:

CIC Filter is like i said before a collection of Integrator Filter equal to a collection of a Comb Filter when Integrators work inside a simple frequency and Comb Filters work inside the same frequency divided by the decimation ratio.

Here is the global RTL of our CIC filter:

We cant talk about CIC filter without mentioned a block named Frequency divider, this one is a generator of clock slower thant our initial clock.

In fact, he is no more than a simple circuit based on a simple  front counter.

Exactly like this Test bench here explain for every 4 initial clock (Red signal) we generate one clock slower edge(blue signal).

To build your own CIC Filter, all what you have to do is to :

1.  Chose N : Filter ordre, (4 in my exemple)
2.  Select R : Decimation ratio. (4 in my exemple)
3.  Build your Integrator stages. 
4.  Build your Comb stages.
5.  Build your frequency Divider block.
6.  build the top level CIC_Filter mapping all those blocks together.

Finite Impulse Response  :FIR Filter

Wikipedia define Fir Filter as a filter whose impulse response (or response to any finite length input) is of finite duration, because it settles to zero in finite time. This is in contrast to infinite impulse response (IIR) filters, which may have internal feedback and may continue to respond indefinitely (usually decaying).

The impulse response (that is, the output in response to a Kronecker delta input) of an Nth-order discrete-time FIR filter lasts exactly N + 1 samples (from first nonzero element through last nonzero element) before it then settles to zero.

FIR filters can be discrete-time or continuous-time, and digital or analog.  

We could simply define it as a low pass filter made using convolution of the inputs signals with their impulse response.

where:

• x[n] is the input signal,
• y[n] is the output signal,
• N is the filter order; a Nth-order filter has (N+1) terms on the right-hand side
• bi is the value of the impulse response at the i’th instant for 0<= i <=N of a Nth-order FIR filter. If the filter is a direct form FIR filter then is also a coefficient of the filter 

So to implement this filter using VHDL all what you have to do is to follow this architecture here :

In your program you have to use an array when you will put inside it your inputs signals delayed to facilate program algorithme.

A simple test bench of our Fir filter give:

We could verify results value by putting somes inputs signals inside a Fir block in Labview or Matlab simulink and comparing it together.

Decimation Filter:

Now after bulding the CIC Filter and the FIR we have just to connect them together to have the final decimation filter.

Here is the top Level RTL of the global Work.

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After bulding and mapping all those blocks together a final test bench give 

Top Level VHDL Code is :

----------------------------------------------------------------------------------
-- Company: 
-- Engineer: 
-- 
-- Create Date:    13:17:33 12/11/2016 
-- Design Name: 
-- Module Name:    Decimation_filter - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity Decimation_filter is
    Port ( Xin : in  STD_LOGIC_VECTOR (7 downto 0);
           Yout : out  STD_LOGIC_VECTOR (7 downto 0);
           clk : in  STD_LOGIC;
     h0: in std_logic_vector(7 downto 0);
     h1: in std_logic_vector(7 downto 0);
     h2: in std_logic_vector(7 downto 0);
     h3: in std_logic_vector(7 downto 0);
           rst : in  STD_LOGIC);
end Decimation_filter;

architecture Behavioral of Decimation_filter is
component FIR port 
(clk: in std_logic;
rst: in std_logic;
x: in std_logic_vector(7 downto 0);
h0: in std_logic_vector(7 downto 0);
h1: in std_logic_vector(7 downto 0);
h2: in std_logic_vector(7 downto 0);
h3: in std_logic_vector(7 downto 0);
y: out std_logic_vector(7 downto 0));
end component;
component comb2 port 
(rst : in  STD_LOGIC;
           clk : in  STD_LOGIC;
           x : in  STD_LOGIC_VECTOR (10 downto 0);
           y : out  STD_LOGIC_VECTOR (9 downto 0));
end component;
component comb3 port 
(rst : in  STD_LOGIC;
           clk : in  STD_LOGIC;
           x : in  STD_LOGIC_VECTOR (9 downto 0);
           y : out  STD_LOGIC_VECTOR (8 downto 0));
end component;
component comb4 port 
(rst : in  STD_LOGIC;
           clk : in  STD_LOGIC;
           x : in  STD_LOGIC_VECTOR (8 downto 0);
           y : out  STD_LOGIC_VECTOR (7 downto 0));
end component;
component comb port 
(rst : in  STD_LOGIC;
           clk : in  STD_LOGIC;
           x : in  STD_LOGIC_VECTOR (11 downto 0);
           y : out  STD_LOGIC_VECTOR (10 downto 0));
end component;
component first_integrator port 
(clk : in  STD_LOGIC;
           rst : in  STD_LOGIC;
           x : in  STD_LOGIC_VECTOR (7 downto 0);
           y : out  STD_LOGIC_VECTOR (8 downto 0));
end component;
component second_integrator port 
(x : in  STD_LOGIC_VECTOR (8 downto 0);
           y : out  STD_LOGIC_VECTOR (9 downto 0);
           clk : in  STD_LOGIC;
           rst : in  STD_LOGIC);
end component;
component third_integrator port 
(clk : in  STD_LOGIC;
           rst : in  STD_LOGIC;
           x : in  STD_LOGIC_VECTOR (9 downto 0);
           y : out  STD_LOGIC_VECTOR (10 downto 0));
end component;
component last_integrator port 
(clk : in  STD_LOGIC;
           rst : in  STD_LOGIC;
           x : in  STD_LOGIC_VECTOR (10 downto 0);
           y : out  STD_LOGIC_VECTOR (11 downto 0));
end component;
component frequency_divider port 
(clk : in  STD_LOGIC;
           rst : in  STD_LOGIC;
           clk_out : out  STD_LOGIC);
end component;


signal aymen1 : std_logic_vector(0 to 8);
signal aymen2 : std_logic_vector(0 to 9);
signal aymen3 : std_logic_vector(0 to 10);
signal aymen4 : std_logic_vector(0 to 11);
signal aymen5 : std_logic;
signal aymen6 : std_logic_vector(0 to 10);
signal aymen7 : std_logic_vector(0 to 9);
signal aymen8 : std_logic_vector(0 to 8);
signal aymen9 : std_logic_vector(0 to 7);
begin
v1:first_integrator port map (clk,rst,Xin,aymen1);
v2:second_integrator port map (aymen1,aymen2,clk,rst);
v3:third_integrator port map (clk,rst,aymen2,aymen3);
v4:last_integrator port map (clk,rst,aymen3,aymen4);
v5:frequency_divider port map (clk,rst,aymen5);
v6:comb port map (rst,aymen5,aymen4,aymen6);
v7:comb2 port map (rst,aymen5,aymen6,aymen7);
v8:comb3 port map (rst,aymen5,aymen7,aymen8);
v9:comb4 port map (rst,aymen5,aymen8,aymen9);
v10:FIR port map (aymen5,rst,aymen9,h0,h1,h2,h3,Yout);
end Behavioral;

If you want to have a copy of any block vhdl code just contact me, Just contact me.

                                                                   

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